A 6b 46GS/s ADC with >23GHz BW and sparkle-code error correction

摘要

This paper presents a 6b 46GS/s 72-way hierarchically time-interleaved asynchronous SAR ADC utilizing cascode samplers to achieve >23GHz BW. A back-end meta-stability correction circuit enables sparkle-code error-free operation over 1e10 samples. The 28nm FDSOI ADC achieves 27dB SNDR (low frequency)/25.2dB (at 23.5GHz) while consuming 381mW from 1.05V/1.6V supplies and occupies 0.14mm.