Investigating the Scalability of Nanowire Junctionless Accumulation Mode FETs using an Intrinsic Pocket

摘要

Nanowire (NW) junctionless accumulation Mode (JAM) FETs were proposed to improve the ON-state current as compared to the conventional junctionless FETs. However, NWJAMFETs suffer from an enhanced detrimental lateral-band-to-band tunneling (L-BTBT) which restricts their scaling to sub-10 nm regime. Therefore, we investigate the scalability of NW JAMFETs using an intrinsic pocket in the extension regions. Using calibrated 3-D simulations, we demonstrate that the incorporation of an intrinsic pocket substantially reduces the L-BTBT induced OFF-state current by around 2 orders and 4 orders of magnitude for a gate length of 20 nm and 7 nm, respectively, leading to a significant ON-state to OFF-state current ratio (I_ON/I_OFF) of 10^{6 and 105, respectively and a small DIBL of 12mV/V and subthreshold swing (SS) of 62.2mV/dec for 20 nm gate length device. The NW JAMFET with intrinsic pocket (P_i-NW JAMFET) exhibits superior short channel characteristics due to the reduced electrostatic source/channel-to-drain coupling and a diminished parasitic BJT action in the sub-10 nm regime extending the roadmap for the device scaling. The proposed P_i-NW JAMFETs show superior performance even at a scaled contacted poly pitch (CPP) of 52 nm with I_OFF~28pA/um for a gate length of 7 nm. The excellent OFF-state characteristics of P_i-NW JAMFET makes them a lucrative FET architecture for realizing sub-10 nm channel lengths for low power and low leakage applications.}