SRAM chips; silicon-on-insulator; SRAM; UTBB FD-SOI; back-bias adjustment; buried oxide; size 28 nm; ultra-thin body; voltage 410 mV; Bit error rate; Built-in self-test; Leakage currents; MOS devices; Random access memory; Transistors; Voltage measurement;
机译:采用28 nm UTBB FD-SOI CMOS技术的6T-SRAM单元尺寸的静态噪声裕度折衷
机译:28nm FD-SOI技术中BTI引起的SRAM阵列动态变化的完整表征和建模
机译:混合GC-eDRAM / SRAM位单元,可实现低功耗运行
机译:使用背栅偏置控制的28nm UTBB FD-SOI技术中的4T,6T,8T,10T SRAM位单元的电路优化
机译:用于28nm 3D CoolCubetm技术的超低电压操作的节能4T基于SRAM位点