Topology-related effects of Gated-V_(dd) and Gated-V_(ss) techniques on full-adder Leakage and Delay at 65nm and 45 nm

摘要

Full-adders are used extensively in most types of digital computing systems. Any design decision made at the full-adder level is likely to have a significant impact on the speed or power consumption of the entire digital system. In this paper, we study how various full-adder topologies are affected by the Gated-V_(dd) and Gated-V_(ss) techniques at 65nm and 45nm, from a leakage power-delay perspective. We observed that most of the circuits studied resulted in leakage-current savings of more than 80% with Gated-V_(dd), incurring a small delay penalty. Delay penalty in case of Gated-V_(dd) is more that of Gated-V_(ss). In Gated-V_(ss). there is a wide variation in leakage power between the topologies studied.