In this paper a new passive Sample and Hold (S/H) structure employing a modified sampling switch circuit has been presented. In order to reach wideband input with high linear sampling, the sampling switch voltage dependency on input signal is reduced, dramatically. Furthermore, the proposed structure reduces signal feedthrough for high frequency inputs as well as enabling the merge of offset cancellation cycle for S/H subsequent stage with the sampling cycle, simultaneously. The simulation results for the designed 12-bit, 250Msps S/H in standard 0.35μm CMOS process with 500MHz input bandwidth, show 14dB and 10dB improvement on THD and signal feedthrough, respectively.
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机译：在本文中，已经介绍了采用改进的采样开关电路的新的无源样本和保持（S / H）结构。为了达到高线性采样的宽带输入，显着降低了输入信号的采样开关电压依赖性。此外，所提出的结构降低了高频输入的信号馈通，以及同时使用采样周期的S / H后续阶段的偏移消除周期的合并。标准0.35μmCMOS工艺中设计的12位，250msps S / H的仿真结果分别具有500MHz输入带宽，显示14dB和10dB的THD和信号馈通的改进。
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