CMOS logic circuits; combinational circuits; delay circuits; digital circuits; optimisation; power consumption; CMOS circuits; combinational circuits; differential delay; digital circuits; dynamic power dissipation estimation; gate inputs; glitch elimination; optimization; power consumption; propagation delay; size 0.8 mum; size 1.2 mum; transmission gate; undesired transition; CMOS integrated circuits; Capacitance; Delays; Inverters; Logic gates; Power dissipation; Propagation delay; Dynamic Power Dissipation; Glitch; Glitch Width; Low power; Propagation delay; Switching Activity; Transmission Gate;
机译:利用分析模型的信号延迟,芯片面积和动态功耗优化高速CMOS逻辑电路
机译:动态可控直流电平转换器(DCLC)技术可减少功耗,并应用于高速,低功率电路
机译:动态可控直流电平转换器(DCLC)技术可减少功耗,并应用于高速,低功率电路
机译:组合电路动态功耗的故障消除与优化
机译:低功耗高带宽芯片设计中的动态CMOS电路功耗方法。
机译:具有实际门延迟模型的CMOS组合逻辑电路的准确动态功率估算
机译:栅极触发:一个新的框架,用于最小化静态CMOS IC中的毛刺功率耗散及其基于ILP的优化