We introduce SiGe FinFET device physics, process integration, and modeling considerations. Germanium is know to have a higher hole mobility than silicon. Enhancement of hole velocity due to lattice mismatch strain in SiGe epitaxy layers is significant. In addition, uniaxial stress is beneficial for device performance. Transformation of biaxial to uniaxial stress naturally occurs when SiGe film is etched into stripes. Furthermore, control of MOSFET threshold voltage by adjusting the SiGe-channel germanium content is possible. On the other hand, SiGe processing challenges include the elimination of interface trap states at the gate dielectric interface, fast diffusion of n-type dopants, and defects in stress relaxed buffer and critical thickness limitations. Band-to-band tunneling sets a lower bound to device static leakage current.
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