DRAM chips; self-adjusting systems; 3D stacked memory design; 3D-stacked DRAM; HMC; data-aware DRAM refresh; data-aware refresh control scheme; data-pattern dependence characteristic; hardware resource; hybrid memory cube; memory bandwidth consumption; power overhead; retention time margin; self-tuning algorithm; synergy testing; trial and error; trial-n-error; weak cell; Benchmark testing; Computer architecture; Radiation detectors; Random access memory; Three-dimensional displays; Tuning;
机译:通过保留时间和双行激活的运行时分析来减少DRAM刷新功耗
机译:屏蔽线对嵌入式应用平面DRAM单元噪声容限和刷新时间的影响
机译:屏蔽线对嵌入式应用平面DRAM单元噪声容限和刷新时间的影响
机译:批量刷新:一种节能技术,可减少混合内存多维数据集体系结构中的刷新开销
机译:具有3D堆叠DRAM的高性能混合存储系统
机译:具有保留功能的DRAM自动刷新方案可提高能源效率和性能
机译:aVaTaR:DRam系统的可变保留时间(VRT)感知刷新
机译:从氢和异氰酸酯反应观察氮杂化物(X立方体倍数,热变化)