A capacitive-coupling technique with phase noise and phase error reduction for multi-phase clock generation

摘要

This paper presents a capacitive-coupling technique for multi-phase oscillators. The proposed capacitive coupling techniques can improve the phase noise performance while maintain good phase accuracy over wide frequency range for multi-phase oscillators. A prototype two-phase VCO is analyzed using injection-locking theory and implemented to demonstrate the effectiveness of the capacitive-coupling technique for low-power and low-noise multiple phase clock generation. The 4.3–5.3 GHz two-phase VCO prototype was implemented in a 130nm CMOS technology and achieved a measured phase noise of −120 to −124.04dBc /Hz @ 1MHz offset and a measured phase error of 0.23–0.91° across the 1GHz tuning range.