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A fully integrated electroencephalogram (EEG) analog front-end IC with capacitive input impedance boosting loop

机译:完全集成的脑电图(EEG)模拟前端IC,具有电容输入阻抗升压环路

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This paper presents a biopotential analog front-end (AFE) IC for measuring electroencephalogram (EEG). The AFE is based on the AC-coupled chopper stabilized instrumentation amplifier architecture to achieve the low noise. To increase the input impedance, the capacitive input impedance boosting loop (CIIBL) is proposed. The CIIBL forms a positive feedback loop between input and output of the instrumentation amplifier without additional power consumption. The CIIBL increases the input impedance from 644 MΩ to 3.5 GΩ, and enhances the CMRR from 133.4 dB to 139.1 dB, in simulation. The overall gain, the frequency response, and the input mismatches can be trimmed using programmable capacitors and programmable resistors. The AFE is fabricated in 0.18 μm 1P6M CMOS process. The core chip size of the AFE without I/O pads is 4000 by 4500 μm. The input referred noise is measured to be 0.205 μV in the bandwidth from 0.5 Hz to 100 Hz. The amplifying gain of the pass band is measured to be 78 dB.
机译:本文介绍了一种用于测量脑电图(EEG)的生物电势模拟前端(AFE)IC。 AFE基于交流耦合的斩波稳定仪表放大器架构,以实现低噪声。为了增加输入阻抗,提出了电容性输入阻抗升压环路(CIIBL)。 CIIBL在仪表放大器的输入和输出之间形成一个正反馈环路,而没有额外的功耗。在仿真中,CIIBL将输入阻抗从644MΩ增加到3.5GΩ,并将CMRR从133.4 dB提高到139.1 dB。整体增益,频率响应和输入失配可以使用可编程电容器和可编程电阻器进行调整。 AFE采用0.18μm1P6M CMOS工艺制造。不带I / O焊盘的AFE的核心芯片尺寸为4000 x 4500μm。在0.5 Hz至100 Hz的带宽内,输入参考噪声的测量值为0.205μV。通带的放大增益测得为78 dB。

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