An overall gain estimation algorithm for all digital phase locked loops

摘要

Fully digital frequency synthesizers are increasingly used in radio frequency (RF) transceivers. The estimation and calibration of the gain for digital controlled oscillator (DCO) and time-to-digital converter (TDC) which is subject to process, voltage and temperature (PVT) variations are important area of research since they can increase the performance and reduce the complexity of the all digital phase locked loops (ADPLL). Normally these two calibration algorithms are implemented separately. In this paper, an overall gain (including DCO gain and TDC gain) tracking algorithm for an ADPLL is presented. The algorithm is based on correlation analysis used in system identification to estimate the unknown impulse response from DCO input to TDC output by applying a training signal. The result shows that with a sufficiently long training sequence, the accuracy of the estimation result will be within a very fine resolution.