TCAD analysis of self-heating effects in bulk silicon and SOI n-MOSFETs

摘要

In this paper we performed 2D and 3D device simulations to analyze the impact of technology scaling on the lattice heating in n-channel bulk silicon and silicon-on-insulator MOS transistors with gate lengths from 0.5 to 0.1 um. Maximum lattice temperatures and transistor thermal resistances for different gate lengths and bias voltages were calculated. The increase in device temperature and thermal resistance with transistor scaling was shown.