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Delay-Driven Layer Assignment in Global Routing under Multi-tier Interconnect Structure

机译:多层互连结构下全局路由中的延迟驱动层分配

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A multilayer routing system usually adopts multiple interconnect configuration with different wire sizes and thicknesses. Since thicker layers of metal lead to fatter wires with smaller resistance, the layer assignment of nets has a large impact on the interconnect delay. However, such layer dependent characteristics have been ignored by most of the state-of-the-art academic layer assignment methods. To remedy this deficiency, this work studies a more effective layer assignment problem under such multi-tier interconnect structure, which arises during 3D global routing and focuses on minimizing both delays and via count. This work presents a two-stage algorithm to solve the problem, which first minimizes the total delay and via count simultaneously by dynamic programming and negotiation technique, and then further minimizes the maximum delay carefully while not increasing the via count. The experimental results on ICCAD09 benchmarks show that the proposed algorithm can significantly reduce the total delay and maximum delay while still keeping roughly the same via count, compared with the state-of-the-art via count minimization layer assignment method NVM.
机译:多层布线系统通常采用具有不同导线尺寸和厚度的多重互连配置。由于较厚的金属层导致电阻较小的较粗的导线,因此网络的层分配对互连延迟有很大的影响。但是,大多数最新的学术层分配方法都忽略了此类依赖于层的特性。为了弥补这一缺陷,这项工作研究了在这种多层互连结构下的更有效的层分配问题,这种问题在3D全局路由过程中出现,并致力于最大程度地减少延迟和通孔计数。这项工作提出了一种两阶段算法来解决该问题,该算法首先通过动态编程和协商技术将总延迟和通孔计数同时最小化,然后在不增加通孔计数的情况下进一步谨慎地使最大延迟最小化。与最新的过孔数量最小化层分配方法NVM相比,在ICCAD09基准上的实验结果表明,该算法可以显着减少总延迟和最大延迟,同时仍保持大致相同的过孔数量。

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