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A fine time-resolution (#x0226A; 3 ps-rms) time-to-digital converter for highly integrated designs

机译:精细的时间分辨率(≪ 3 ps-rms)时间数字转换器,用于高度集成的设计

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A multi-channel 3-ps-rms single-shot precision timeto-digital converter (TDC) is presented. The time interpolation is based on a delay-locked-loop (DLL) employing resistive interpolation to achieve least-significant-bit (LSB) sizes as small as 5 ps. To calibrate out device mismatches, only the timing-reference signals need to be calibrated. The usual need for calibrating each channel individually is avoided. After calibration, the measured differential-non-linearity (DNL) and integral-non-linearity (INL) are ±0.9 LSB and ±1.3 LSB respectively. A prototype, implemented in a commercial 130 nm technology, consumes between 34mW to 42 mW/channel and shows a voltage sensitivity of -0.19 ps/mV and a temperature dependence of 0.44 ps/°C. To the best of our knowledge this is the first time a TDC demonstrates single-shot precisions on multiple channels smaller than 3ps-rms.
机译:提出了一种多通道3-ps-rms单次精密时间数字转换器(TDC)。时间插值基于采用电阻插值的延迟锁定环(DLL),以实现低至5 ps的最低有效位(LSB)大小。要校准设备不匹配,只需校准时序参考信号。避免了通常需要分别校准每个通道的情况。校准后,测得的差分非线性(DNL)和积分非线性(INL)分别为±0.9 LSB和±1.3 LSB。采用商用130 nm技术实现的原型,每通道功耗在34mW至42 mW之间,电压灵敏度为-0.19 ps / mV,温度依赖性为0.44 ps /°C。据我们所知,这是TDC首次在小于3ps-rms的多个通道上演示单次发射精度。

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