Application of Fast Wafer-Level Reliability PBTI Tests for Screening of High-k/Metal Gate Process Splits

摘要

This work shows how fast wafer-level reliability (fWLR) inline tests allow to quickly screen the intrinsic reliability of High-k/Metal Gate (HK/MG) process splits in an effective manner. Various Hf based gate stack compositions such as pure HfO_2, Hf_xZr_(1-x)O_2 and Hf_xZr_(1-x)O_2 are investigated from a reliability point of view. The main focus lies on PBTI (positive bias temperature instability) which is one of the most critical reliability concerns in current HK/MG stacks. As a key result, PBTI was found to improve when doping the HfO_2 with either silicon or zirconium. Since HK/MG technology also introduces more process parameters to be controlled, it is shown that with fWLR tests implemented in a wafer electrical test environment their influence on reliability can be evaluated much faster than with standard lab approaches.