Modeling the Hysteresis of Current-Voltage Characteristics in 4H-SiC Transistors

摘要

4H-SiC MOSFETs exhibit a hysteresis of the transfer characteristics due to electrically active traps near the $mathrm{S}mathrm{i}mathrm{C}/mathrm{S}mathrm{i}mathrm{O}_{2}$ interface. Our measurements, conducted within the temperature range of 150-260K revealed an interesting behavior, namely a notable decreasing hysteresis width towards higher T. During the up-sweep of gate voltage $V_{mathrm{g}mathrm{s}}$ curves are shifted towards higher gate voltages compared to the curves acquired at the down-sweep of $V_{mathrm{g}mathrm{s}}$. This implies that more traps are negatively charged at higher $V_{mathrm{g}mathrm{s}}$ conditions, and we attribute this behavior to acceptor-like border traps in oxide having its charge transition level 0/-1 near the SiC conduction band edge. To model electron capture and emission events of these oxide traps, we use the non-radiative multiphonon model. We calculate the capture and the emission times. The temperature dependence of the latter is the dominant feature which decreases the hysteresis width with increasing T. Our modeling approach is capable of reproducing the hysteresis width over the measured T range with good accuracy.