The memory architecture design of FC-AE-1553 chip

摘要

The memory architecture design and effective management is the key factor to the widely use of the FC-AE-1553 chip. On the basis of analyzing the FC-AE-1553 chip features, a kind of memory architecture with the characteristics of shared storage, circular storage, and global double buffering mechanism has been presented. This paper describes the implementation of the memory architecture in detail from the perspective of the NC and NT, respectively. By testing on the co-verification platform of the hardware and software in practical, the experimental results show that the chip memory architecture improves the efficiency of the data storage in the high-speed environment greatly and provides an important basis for the realization and the miniaturization of the FC-AE-1553 chip.