A Fast-Locking All-Digital Phase-Locked Loop with a Novel Counter-Based Mode Switching Controller

摘要

Settling time is a crucial design issue in Phase-Locked Loop (PLL) used in modern wireless communication systems. A Digitally Controlled Oscillator (DCO)-based multi-operational modes All-Digital PLL (ADPLL), which can achieve an ultra fast settling time of 10 μs, has been intensively researched. This paper describes a novel Counter-Based Mode Switching Controller (CB-MSC) for the ADPLL to further reduce its settling time. By monitoring the variation of DCO Tuning Word (OTW), the CB-MSC can control the ADPLL to switch from one operational mode to another quickly, which significantly reduce the mode switching time. An estimated OTW for presetting the DCO is also generated by the CB-MSC to accelerate the frequency acquisition process. The proposed ADPLL was designed in VHDL and simulated in ModelSim environment. Simulation results demonstrate that a minimum settling time of 5.7 μs is achieved and the average improvement factor is 37.8%.