Statistical optimization of process parameters for threshold voltage in 22 nm p-Type MOSFET using Taguchi method

摘要

This paper aims to study the effect of process parameter variation on a nano-scaled planar p-type MOSFET (metal-oxide-semiconductor field-effect transistor) device for 22 nm technology using Taguchi's L9 orthogonal array. The device was constructed with high-k/metal gate consisting of Titanium dioxide (TiO) and Tungsten silicide (WSix) metal gate using an industrial-based numerical simulator. Using Taguchi's Signal-to-noise ratio (SNR) of nominal-the-best (NTB), the compensation implantation has been as identified as the dominant factor influencing the Vth value with 67.77% while the Halo implantation tilting angle has been identified as the adjustment factor. Upon optimization, the V value is -0.29538 V which is within the requirements of the International Technology Roadmap for Semiconductors (ITRS) 2012 which is -0.289 V ± 12.7 %.