Differential Power Analysis (DPA) side-channel attacks pose serious threats for embedded system security. WDDL was proposed as a countermeasure that can be incorporated into a conventional ASIC design flow using standard cells. However, our spice simulations show that DPA attacks on WDDL still leak secret keys to adversaries despite the doubled area and energy overheads due to the use of complementary cells. This paper proposes ExCCel, a simulated annealing based method that automatically generates and explores combinations of complementary cells for reducing the power-consumption dependency and overheads using standard cells. Our experimental results on the AES S-Box circuit with our explored complementary cells requires 6.1% and 2.1% additional area and energy while WDDL requires 100.3% and 93.4%, respectively. Moreover, ExCCeL achieves higher DPA attack resistivity compared to WDDL in many cases.
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