Deformations of metal interconnects, cracks in interlayer dielectrics and passivation layers in combination with plastic packaging are still a major reliability concern for integrated circuit power semiconductors. In order to describe and understand the failure mechanism and its root cause, already a lot of work has been done in the past. However for the first time the impact of the leadframe profile on the amount of electrical failures after thermal cycling (TC) was investigated in detail. It was found that with a trench in the leadframe on the perimeter of the Si die with the power switching device, the number of electrical failures have been eliminated completely. The observation is confirmed by 3-D Finite Element Modeling (FEM) simulation. The simulation enabled to quantify the stress level and to forecast corresponding electrical failures observed after temperature cycling. As a result, an improved leadframe design could be deduced, which led to a distinct reduction of the principal stress at the most critical positions and, consequently, to an improvement of the reliability of the devices.
展开▼
