An auxiliary switched-capacitor power converter (SCPC) applied in stacked digital architecture for energy utilization enhancement

摘要

Reducing the supply voltage of digital circuit to its sub-or near-threshold region is critical for achieving minimum energy point (MEP) operation. However, as the supply voltage on the load is lowered, the overall efficiency of conventional circuit architecture using DC-DC converter also decreases. In this work, we demonstrate a stacked load architecture regulated by an auxiliary switched-capacitor power converter (SCPC) to achieve ultra-low power regulation of load supply voltage. We further show that the self-restoring behavior of MEP operation can also be leveraged in our design for achieving high-efficiency supply voltage regulation. As an example, we implement our design with a standard 0.18 μm CMOS process in a 4-stacked structure, with each stacked load cell operating at 450 mV in its sub-threshold region and fully functioning. While the current regulating capability of the SCPC is designed to be only 10% of the load current to match the load current difference, the load voltage can be regulated with more than 99% precision. We achieve an overall energy efficiency of >94% for the entire system.