Monolithic three-dimensional (3D) integrated circuits (ICs) achieve ultra-high density device integration through fine-grained connectivity enabled by monolithic inter-tier vias (MIVs). In this paper, an open source standard cell library for design automation of large-scale transistor-level monolithic 3D ICs is proposed. A 128-point, highly parallelized FFT core with 330K cells is implemented with the proposed library. Power and timing characteristics of monolithic 3D ICs are quantified. The effect of signal integrity and routing congestion on timing characteristics is investigated. The primary clock tree characteristics of monolithic 3D ICs are also discussed. The proposed open source cell library facilitates future research on multiple aspects of monolithic 3D technology.
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