A 6mW 480MHz Continuous Time (SIGMA)(DELTA) Modulator with 65dB DR over 5MHz Bandwidth in 65nm CMOS

摘要

A second order, single-bit CT (SIGMA)(DELTA) ADC with 480MHz sampling frequency and 5MHz input signal bandwidth is presented. The ADC achieves 65dB DR in 65nm standard digital CMOS technology. The proposed implementation has a highly optimized quantizer, feedback path and clock circuitry leading to 4mA of current consumption and 0.11mm~(2) of area. The Figure of Merit for the design is 0.478pJ/conv.