A 100 (mu)W Decimator for a 16 bit 24 kHz bandwidth Audio (DELTA)(SIGMA) Modulator

摘要

A decimation filter for a low power Delta Sigma ((DELTA)(SIGMA)) modulator with 24 kHz bandwidth and an in band resolution of 16 bits is designed with standard cells in a 1.8 V, 0.18 (mu)m CMOS process. Retiming, Canonical Signed Digits (CSD) encoding along with optimal selection of data width are coded with a hardware description language (HDL) to obtain optimality for power and an automated design. The filter occupies an area of 0.46 mm~(2) and consumes 100(mu)W from a supply of 1.8 V and is operational down to a supply voltage of 0.9 V. This makes it suitable for use with very low power (DELTA)(SIGMA) data converters for digital audio.