2.4GHz ZigBee Radio Architecture with Fast Frequency Offset Cancellation Loop

摘要

This paper describes a radio architecture with fast analog frequency offset cancellation loop which is based on a ΣΔ fractional-N frequency synthesizer and a frequency offset detector. The offset detector is composed of a Frequency/Phase Detector (PFD) and a new non-uniform resolution Time-to-Digital Converter (TDC). By adopting the weighted delay-length for the TDC, only 60-DFFs are used to generate digitized timing difference of 250ns with a minimum resolution of 1ns. For the 2.4GHz ZigBee transceiver with 4MHz IF, designed for 0.18μm CMOS process, the frequency offset cancellation time takes about 30μs under the PLL loop-bandwidth of 100 kHz.