A high-speed Reed-Solomon decoder for correction of both errors and erasures

摘要

This paper presents the design of a (n,k) Reed-Solomon decoder for both errors and erasures. The key-equation solver is based on Sarwate's reformulated inversionless Berlekamp-Massey algorithm. The decoder has been implemented on FPGA and the maximum clock frequency can be 150 MHz for a (255, 239) code on a Xilinx Virtex-II device.