This paper presents a wavelet based event detector for cardiac pacemakers implemented in 0.35μm CMOS technology. The architecture is optimized by wordlength and strength reduction resulting in a total chip area of 2.2mm{sup}2. Detector performance is studied by means of databases containing electrograms as well as different types of noise and interferences, which are added to the signals. The results show that reliable detection can be obtained for moderate to high noise levels, whereas the architecture of the implemented detector is optimized to meet low power constraints implemented in digital hardware.
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