This work presents a low-voltage CMOS amplifier. The amplifier combines a p-channel differential input pair and a level-shift p-channel differential input pair to obtain rail-to-rail signaling. Simulations using a 0.3Sum 2p4m CMOS process at IV supply voltage, the amplifier performs 76 dB dc gain, 5.27 MHz unit-gain bandwidth, 288uW power dissipation and 84° phase margin at 15 pF output load.
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机译：这项工作介绍了低压CMOS放大器。放大器组合了P沟道差分输入对和电平移位P沟道差分输入对以获得轨到轨信令。使用0.3Sum 2P4M CMOS工艺在IV电源电压下模拟，放大器执行76 dB DC增益，5.27MHz单元增益带宽，288UW功耗和15个PF输出负载的84°相余量。
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