An Area-Efficient Word-line Pitch-aligned 8T SRAM Compatible Digital-to-Analog Converter

摘要

Area and energy-efficient data converters are an integral part of In-Memory Compute (IMC) engines. The conventional Digital to Analog Converters (DACs) uses binary-weighted pull-up current sources with scan-flops feeding in the digital input. These bulky pull-up devices and scan-flops make it hard to integrate along-side a memory array in an area-efficient manner. Further, it is prone to error due to local variations owing to limited digital control. In this paper, we propose an area-efficient, Word-Line (WL) pitch-aligned, layout friendly In-Memory compatible DAC (IM-DAC), whose layout resembles the 8T SRAM array very closely, thus achieving memory array-like density. Simulation results show that the worst-case INL and DNL is 2.42 LSB and -0.32 LSB, respectively. We obtained a 3.4X area advantage in comparison with the conventional DAC. The high-density layout allows for additional calibration pull-up stacks, with minimal area penalty, that reduces the standard deviation of the linearized-current to 48.76% of the corresponding value before calibration.