AREA-EFFICIENT DUAL-PORT AND MULTI-PORT SRAM. AREA-EFFICIENT MEMORY CELL FOR SRAM

摘要

The present disclosure relates to a static random access memory and a memory cell for a static random access memory, the memory cell comprising: a first transistor (M1), a second transistor (M2), a third transistor (M3) and a fourth transistor (M4) forming first and second cross-coupled inverters (INV1, INV2), wherein the first and second cross-coupled inverters (INV1, INV2) define a first storage node (D) and an inverted first storage node (D'), wherein the first inverter (INV1) is connected to a first reference voltage (GND1) and a first supply voltage (VDD1), and wherein the second inverter (INV2) is connected to a second reference voltage (GND2) and a second supply voltage (VDD2); a fifth transistor (M5) connected between the first storage node (D) and a first bit line (BL1); a sixth transistor (M6) connected between the inverted first storage node (D') and a second bit line (BL2); a first word line (WL1) connected to the fifth transistor (M5), said first word line (WL1) controlling the access of the first bit line (BL1) to the first storage node (D); and a second word line (WL2), independent of the first word line (WL1), connected to the sixth transistor (M6), said second word line (WL2) controlling the access of the second bit line (BL2) to the inverted first storage node (D') independently of the first bit line (BL1); wherein relative voltage levels of the first word line (WL1) and first reference voltage (GND1), or of the first supply voltage (VDD1) and the first reference voltage (GND1), or of the second word line (WL2) and second reference voltage (GND2), or of the second supply voltage (VDD2) and the second reference voltage (GND2), or of the first reference voltage (GND1) and the second reference voltage (GND2) are configured such that data of the first storage node (D) and the inverted first storage node (D') can be read and written independently.