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Area-efficient dual-port and multi-port SRAM. Area Efficient Memory Cells for SRAM

机译:区域高效的双端口和多端口SRAM。 用于SRAM的区域高效存储器单元

摘要

The present disclosure relates to a static random access memory and a memory cell for a static random access memory, the memory cell comprising: a first transistor (M1) forming first and second cross-coupled inverters (INV1, INV2); A second transistor M2, a third transistor M3 and a fourth transistor M4, wherein the first and second cross-coupled inverters INV1, INV2 are connected to a first storage node D and an inverted first transistor M4. A first storage node D' is defined, a first inverter INV1 is connected to a first reference voltage GND1 and a first supply voltage VDD1, and a second inverter INV2 is connected to a second reference voltage GND2 ) and connected to a second supply voltage (VDD2); a fifth transistor M5 connected between the first storage node D and a first bit line BL1; a sixth transistor M6 connected between the inverted first storage node D′ and a second bit line BL2; A first word line WL1 connected to the fifth transistor M5, the first word line WL controls access of the first bit line BL1 to the first storage node D ; In addition, a second word line WL2 independent of the first word line WL1 and connected to the sixth transistor M6 and the second word line WL2 are connected to the first bit line BL1 and independently controlling access of the second bit line (BL2) to the inverted first storage node (D'); Relative voltage levels of the first word line WL1 and the first reference voltage GND1 or relative voltage levels of the first supply voltage VDD1 and the first reference voltage GND1 , or relative voltage levels between the second word line WL2 and the second reference voltage GND2 , or relative voltage levels between the second supply voltage VDD2 and the second reference voltage GND2 , or The relative voltage levels of the first reference voltage GND1 and the second reference voltage GND2 allow the data of the first storage node D and the inverted first storage node D′ to be independently read and written. is configured to
机译:本公开涉及一种静态随机存取存储器和用于静态随机存取存储器的存储器单元,存储器单元包括:形成第一和第二交叉耦合逆变器的第一晶体管(M1)(INV1,INV2);第二晶体管M2,第三晶体管M3和第四晶体管M4,其中第一和第二交叉耦合反相器INV1,INV2连接到第一存储节点D和反转的第一晶体管M4。定义第一存储节点D',第一逆变器INV1连接到第一参考电压GND1和第一电源电压VDD1,第二逆变器INV2连接到第二参考电压GND2并连接到第二电源电压( VDD2);连接在第一存储节点D和第一位线BL1之间的第五晶体管M5;连接在反相第一存储节点D'和第二位线BL2之间的第六晶体管M6;第一字线WL1连接到第五晶体管M5,第一字线WL控制第一位线BL1的访问到第一存储节点D;另外,独立于第一字线WL1并连接到第六晶体管M6和第二字线WL2的第二字线WL2连接到第一位线BL1并独立地控制第二位线(BL2)的访问到倒第一存储节点(D');第一字线WL1的相对电压电平和第一电源电压Vdd1的第一参考电压GND1或第一参考电压GND1的相对电压电平,或第二字线WL2和第二参考电压GND2之间的相对电压电平,或第二电源电压VDD2和第二参考电压GND2之间的相对电压电平,或第一参考电压GND1和第二参考电压GND2的相对电压电平允许第一存储节点D和反转的第一存储节点D'的数据独立阅读和书面。配置为

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