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Area-efficient dual-port and multi-port SRAM. Area Efficient Memory Cells for SRAM
Area-efficient dual-port and multi-port SRAM. Area Efficient Memory Cells for SRAM
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机译:区域高效的双端口和多端口SRAM。 用于SRAM的区域高效存储器单元
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摘要
The present disclosure relates to a static random access memory and a memory cell for a static random access memory, the memory cell comprising: a first transistor (M1) forming first and second cross-coupled inverters (INV1, INV2); A second transistor M2, a third transistor M3 and a fourth transistor M4, wherein the first and second cross-coupled inverters INV1, INV2 are connected to a first storage node D and an inverted first transistor M4. A first storage node D' is defined, a first inverter INV1 is connected to a first reference voltage GND1 and a first supply voltage VDD1, and a second inverter INV2 is connected to a second reference voltage GND2 ) and connected to a second supply voltage (VDD2); a fifth transistor M5 connected between the first storage node D and a first bit line BL1; a sixth transistor M6 connected between the inverted first storage node D′ and a second bit line BL2; A first word line WL1 connected to the fifth transistor M5, the first word line WL controls access of the first bit line BL1 to the first storage node D ; In addition, a second word line WL2 independent of the first word line WL1 and connected to the sixth transistor M6 and the second word line WL2 are connected to the first bit line BL1 and independently controlling access of the second bit line (BL2) to the inverted first storage node (D'); Relative voltage levels of the first word line WL1 and the first reference voltage GND1 or relative voltage levels of the first supply voltage VDD1 and the first reference voltage GND1 , or relative voltage levels between the second word line WL2 and the second reference voltage GND2 , or relative voltage levels between the second supply voltage VDD2 and the second reference voltage GND2 , or The relative voltage levels of the first reference voltage GND1 and the second reference voltage GND2 allow the data of the first storage node D and the inverted first storage node D′ to be independently read and written. is configured to
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