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28nm high-k metal gate RRAM with fully compatible CMOS logic processes

机译:具有完全兼容CMOS逻辑工艺的28nm高k金属栅极RRAM

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A new 2-transistor logic ReRAM cell with 28nm high-k metal gate (HKMG) and fully CMOS logic compatible process is reported. The new 28nm logic compatible RRAM cell consists of two logic standard high-k metal gate CMOS transistors by an optimized composite resistive gate dielectric film TiN/HfO2/TiN as a storage node in the cell and as a gate dielectric in the select transistor. Using the cell gate as a source line for RRAM set/reset operation, the resistive memory states can be read and sensed by the selection of the select transistor and its bitline. As a result, the new 2-transistor CMOS logic ReRAM cell is very area-saving, cost effective, and fully compatible with advanced high-k metal gate CMOS logic technology platform. By adapting the highly manufacturable high-K gate dielectric in embedded ReRAM cell, the cell does not need any additional deposition of the resistive film or extra process steps, as a result, it will be easily scaled down and following by the CMOS technology evolution, besides it can be simply dropped on a logic IP or circuits for the need of NVM array or discrete storages in advanced SOC logic-NVM applications.
机译:报道了一种新的具有28nm高k金属栅极(HKMG)和完全CMOS逻辑兼容工艺的2晶体管逻辑ReRAM单元。新的28nm逻辑兼容RRAM单元由两个逻辑标准的高k金属栅极CMOS晶体管组成,该晶体管通过优化的复合电阻栅介质膜TiN / HfO 2 / TiN作为单元中的存储节点和选择晶体管中的栅极电介质。使用单元栅极作为RRAM设置/复位操作的源极线,可以通过选择晶体管及其位线的选择来读取和感测电阻式存储器的状态。因此,新型2晶体管CMOS逻辑ReRAM单元非常节省面积,具有成本效益,并且与先进的高k金属栅极CMOS逻辑技术平台完全兼容。通过在嵌入式ReRAM单元中采用高度可制造的高K栅极电介质,该单元不需要任何额外的电阻膜沉积或额外的处理步骤,因此,随着CMOS技术的发展,它很容易按比例缩小,此外,可以将其简单地放在逻辑IP或电路上,以满足高级SOC逻辑NVM应用中NVM阵列或离散存储的需要。

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