Timing Violation as Dominant Reason for Failure of Clocked Digital Circuit Due to RF Interference in Supply

摘要

This paper covers our observations of the failure behavior of a clocked digital circuit with sinusoidal interference acting on its supply. Conventionally, it has been thought that interference causes mainly logic-level errors in digital circuits, with the average value of the interference determining the circuit delay. As the interference cycle time is much shorter than both the data path delay and clock cycle time, the average value of the interference is almost zero. However, it still causes a timing violation, rather than a logic-level error, in the circuit. This observation was at odds with conventional thinking. This behavior was confirmed with both transistor-level simulations and board-based measurements. The findings of the present study are important for determining the frequency response of the maximum tolerable interference amplitude of a digital circuit in the design phase