Supporting Ordered Multiprefix Operations in Emulated Shared Memory CMPs

摘要

Shared memory emulation is a promising technique to address programmability and performance scalability concerns of chip multiprocessors (CMP) because it provides implied synchrony in execution of machine instructions, efficient latency hiding technique, and enough effective bandwidth to route all the memory references even with the heaviest workloads. In our earlier research we have proposed an architectural solution to support concurrent memory access and multioperations on emulated shared memory CMPs with a help of active memory units attached to memory modules. While this solution provides faster memory access than other known solutions with minor silicon area and power consumption overlieads, the results of multiprefixes are unfortunately not in order forcing one to use a relatively slow logarithmic multiprefix algorithm for ordered multiprefixes. In this paper we propose an architectural technique for supporting a limited number of concurrent ordered multiprefix operations in emulated shared memory CMPs. Tlie solution is based on adding special multiprefix arrays to active memory units. Performance, silicon area, and power consumption evaluations are given.