The Design and Implementation of Configurable Symbol Synchronization Based on FPGA

摘要

In many synchronous receivers, symbol timing synchronization is achieved through implementation of an analog phase locked loop (PLL). A phase detector and voltage-controlled oscillator drive a reference signal to be in phase with the received training sequence. Due to the quick phase convergence this option is attractive, however, limitations in pre-packaged hardware make this approach infeasible at times. This paper examines a configurable symbol synchronizer Based on Digital Phase Locked Loop (DPLL). We implement this method with FPGA. This method firstly gets the phase difference between the local synchronization signal and the received symbols by XOR. Then using the phase difference controls the counter. The counter controls the number of adding or deleting pulses in the corresponding gate. The synchronization time can be changed through setting of different K so as to achieve the purpose of fast bit synchronization. The paper shows the feasibility of this architecture can obviously decrease the synchronization time.