High Performance Pipelined Signed 64x64-Bit Multiplier Using Radix-32 Modified Booth Algorithm and Wallace Structure

摘要

This paper manly focus on enhancing speed performance of signed multiplication using radix-32 modified Booth algorithm and Wallace Structure. It is designed for fixed length 64x64 bit operands. 3:2and 4:2 Compressor used in Wallace tree structure accumulate partial products. Using both compressor, No. of levels has been reduced that also causes enhancing the speed of multiplier. An efficient VHDL code has been written and successfully synthesized and simulated using Xilinx ISE 9.2i and Model Sim PE Student Edition 10.2c. Proposed pipelined signed 64x64 bit multiplier using radix-32 Booth algorithm and Wallace tree structure provides less delay 1.4 ns and required 87% less number of levels in Wallace tree structure, 76% less total number of Compressor, 70% less generated partial products as compared to conventional multipliers.