Clock synchronisation in multi-transceiver HF radar system

摘要

The TIGER-3 radar is being developed as an “all digital” radar with 20 integrated digital transceivers, each connected to a separate antenna. Accurate coordination of all 20 transceivers is essential for both generation of transmit signals and collection and merging of receive data to form a standard Su-perDARN data set. This paper proposes a clock synchronisation method to coordinate the operation of the entire system using Field Programmable Gate Array (FPGA) technology. The method is a co-operation between hardware and software to achieve the necessary clock quality and synchronisation requirements. It is extremely important that the clock signals are kept aligned in time within specified bounds. To achieve this a 125Mhz common master clock is sent from a clock controller to a clock buffer, which then distributes the signals to the transceivers. In turn, each transceiver sends back a clock signal which is a buffered version of the common clock in the same bundle. In order to synchronise clocks on the transceivers, phase delays of round-trip clock paths are measured on the clock controller board with the accuracy of 31.25ps. The measurement is performed by shifting the common clock phase at a resolution of 1/256 of the clock period until the return clock and the common clock are in phase. Once the measurement cycle is complete, each transceiver adjusts the phase of its clock as directed by the clock controller. Experimental results show that the phase noise of the transmit signal generated from the synchronised clocks at transceivers is less than −100 dBc/Hz, while the SNR of the transmit signal is ≈ 90 dB for the entire 8–20 MHz range.