A 0.63ps resolution, 11b pipeline TDC in 0.13µm CMOS

摘要

This paper presents the first pipeline TDC based on time-domain 1.5b MDAC stages with a digital-domain residue calibration and a time amplifier gain calibration. The proposed architecture is implemented with an 11b TDC using a 0.13µm CMOS. The TDC achieves the finest 1b resolution of 0.63ps ever reported in a conversion range of 1.3ns, DNL of ±0.5LSB, and INL of ±2LSB.