A new four-port de-embedding procedure based on the transmission-line theory for on wafer S-parameter measurement is demonstrated in this paper for the first time. Although the traditional open and short test structures can characterize the resistive and inductive properties of the parasitic effects of the metal interconnect lines, the conductive and capacitive characteristics are hardly eliminated only with lumped equivalent circuit models in high substrate loss CMOS process. In this paper, we employed the transmission-line based technique to accurately remove not only the resistive and inductive parasitic effects but also the conductive and capacitive ones in the four-port measurement. We only used one simple open and one through test structures to remove the unwanted parasitic effects from pads and interconnects. In addition, the poly ground-shielded technology was adopted underneath the pads to reduce the parallel parasitic capacitance of shielded-based test structures without influencing the isolation between the signal ports in this work. This de-embedding methodology for extracting the four-port MOSFET parameters including the substrate network can be realized up to 10 GHz operating frequency in this work. In addition, in comparison with the traditional four-port open-short de-embedding procedure, the greatest advantage of our proposed method is the significant chip area reduction, and we expect to construct equivalent circuit models for different dimensions and bias through our proposed de-embedding method for future rf circuit designers.
展开▼
