A low power 12-bit 10MS/s algorithmic ADC

摘要

A low power 12-bit 10MS/s algorithmic analog-to-digital converter (ADC) utilizing capacitor sharing and capacitor scaling techniques is presented. The techniques greatly reduce the power consumption of a typical algorithmic ADC. Power estimates are derived for the proposed technique, and other low power techniques. Circuit implementation details are presented along with simulated results. The ADC is expected to achieve a signal-to-noise-and-distortion ratio (SNDR) of 66dB while consuming 1mW from a 1.5V supply.