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Circuits, architectures, apparatuses, systems, algorithms, and methods for memory with multiple power supplies and/or multiple low power modes

机译:用于具有多个电源和/或多个低功率模式的存储器的电路,架构,装置,系统,算法和方法

摘要

Circuits, architectures, a system and methods for memories with multiple power supplies and/or multiple low power modes. The circuit generally includes peripheral circuitry operating at a first voltage, a memory array operating at a second voltage, and translation circuitry configured to receive an input from the peripheral circuitry at the first voltage and provide an output to the memory array at the second voltage, the translation circuitry further configured to prevent leakage during a standard operating mode of the memory. The method generally includes operating peripheral circuitry at a first voltage from a first power rail, operating a memory array at the first voltage or a second voltage, the memory array being coupled to a second power rail, coupling the first and second power rails during standard operating mode when the memory array operates at the first voltage, otherwise not coupling the first and second power rails, and reducing leakage in the memory array during a leakage reduction mode by reducing a voltage differential between a ground plane in the memory array and the second power rail.
机译:用于具有多个电源和/或多个低功率模式的存储器的电路,架构,系统和方法。该电路通常包括在第一电压下工作的外围电路,在第二电压下工作的存储器阵列以及配置为在第一电压下接收来自外围电路的输入并在第二电压下向存储器阵列提供输出的转换电路。转换电路还被配置为在存储器的标准操作模式期间防止泄漏。该方法通常包括以来自第一电源轨的第一电压操作外围电路,以第一电压或第二电压操作存储器阵列,该存储器阵列耦合到第二电源轨,在标准期间耦合第一和第二电源轨。当存储器阵列在第一电压下操作时处于工作模式,否则不耦合第一和第二电源轨,并且通过减小存储器阵列中的接地平面与第二阵列之间的电压差来减少泄漏减少模式期间存储器阵列中的泄漏电源导轨。

著录项

  • 公开/公告号US9570118B2

    专利类型

  • 公开/公告日2017-02-14

    原文格式PDF

  • 申请/专利权人 MARVELL INTERNATIONAL LTD.;

    申请/专利号US201514957029

  • 发明设计人 HA SOO KIM;WINSTON LEE;

    申请日2015-12-02

  • 分类号G11C8/08;G11C5/14;G11C7/02;

  • 国家 US

  • 入库时间 2022-08-21 13:45:08

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