Overcoming the unselected pin relay capacitance HBM tester artifact with two pin HBM testing

摘要

HBM tester parasitic capacitances are shown to degrade the current pulse rise-times on the ground path return. Rise-times longer than allowed in the HBM specification may cause failures on devices with transiently triggered ESD protection networks. Two pin HBM testing and TLP measurements have verified such failures as being induced by tester parasitics. Updates to the HBM standard are needed to address this testing issue.