Escaped errors in released silicon are growing in number due to the increasing complexity of modern processor designs and shrinking production schedules. Worsening the problem are recent trends towards chip multiprocessors (CMPs) with complex and sometimes non-deterministic memory subsystems prone to subtle, devastating bugs. This deteriorating situation is causing a growing portion of the validation effort to shift to post-silicon, when the first few hardware prototypes become available and where validation experiments are run directly on newly manufactured prototype hardware. While post-silicon validation enables much higher raw performance in test execution, it is a much more challenging environment for bug diagnosis and correction. In this work we briefly overview some of the current methodologies used in industry. We then discuss some recent ideas developed in our research group to leverage the performance advantage of post-silicon validation, while sidestepping its limitations of low internal node observability and expensive bug fixing. Finally we present some of today's general trends in post-silicon validation research.
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