DRAM APPARATUS AND METHOD OF DEBUGGING POST SILICON USING ON-CHIP DRAM FOR MULTI-CORE DESIGN

摘要

The present invention relates to a technique for selectively debugging only data estimated to be an error in post silicon debugging in a multicore environment using an on-chip DRAM, wherein a method of debugging post silicon according to an embodiment includes: The method of claim 1, further comprising the steps of: generating golden data corresponding to the detected error intervals and uploading the generated golden data to a trace buffer to identify error intervals in the debug interval; And selectively debugging the error data corresponding to the error cycle.