DRAM APPARATUS AND METHOD OF DEBUGGING POST SILICON USING ON-CHIP DRAM FOR MULTI-CORE DESIGN

摘要

The present invention relates to a technology for selectively debugging only data estimated as an error during post silicon debugging in a multi-core environment using an on-chip DRAM. According to an embodiment of the present invention, a post silicon debugging method comprises the steps of: verifying error sections of a dubbing section by generating golden data corresponding to the debugging section based on a simulation before debugging, and uploading the generated golden data on a trace buffer; detecting an error cycle corresponding to the verified error sections; and selectively debugging error data corresponding to the detected error cycle.