A fast and highly accurate path delay emulation framework for logic-emulation of timing speculation

摘要

This paper proposes a novel path-delay fault emulation technique called Replay. We specifically show it allows FPGA emulation of digital ICs that adopt timing-speculation techniques. For each flip-flop, Replay builds a timing-error predictor based on timing-speculation's aggressive clock period. We use a heuristic which replicates the combination logic and uses path delays to determine which paths will be excited based on the aggressive clock period. The timing-error prediction accuracy is more than 99% for a set of real workloads on the OpenRISC processor and the FPGA emulation speed shows practically no slowdown. We also demonstrate that Replay can evaluate the impact of voltage-drop timing-faults. This fast and accurate timing-error prediction enables practical emulation of timing-speculation and quantitative analysis early in the design-cycle.