In this paper, a new model for interleaved planar symmetric balun in CMOS radio frequency integrated circuits (RFICs) is developed. The model uses a “2-Π” sub-circuit to represent each inductor coil in the balun, and a novel substrate inductance is introduced to describe the substrate eddy-current effect. Verification with the measured data from a CMOS process demonstrates the model''s accurate performance prediction up to self-resonant frequency (SRF).
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