Experiment and simulation of transistor level fault model of IDDT test

摘要

Fault and fault model is the fundament of IC diagnosis. Fault model based on IDDT and its test is the hot issue of modern IC fault diagnosis at present. Open and short fault models of inverter, NAND gate, and SRAM of CMOS technology were built in this paper. In the experiments, we selected the deep sub-micron of 0.18 μm CMOS technology to simulate with HSPICE. The simulations of IDDT waveforms and FFT transform waveforms of different fault models were made and the results were indicated that the IDDT test method can detect the open and short fault of CMOS devices effectively.