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Economic Assessment of Lithography Strategies for the 22nm Technology Node

机译:22nm技术节点光刻技术的经济评估

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The unavailability of extreme ultra violet lithography (EUVL) for mass production of the 22nm technology node has created a significant void for mainstream lithography solutions. To fill this void, alternate lithography solutions that were earlier deemed to be technically and economically infeasible, such as double patterning technologies (DPT), source mask optimization (SMO), massively parallel direct write e-beam (MEBM) and Interference assisted lithography (Intf), are being proposed, developed and adopted to ensure the timely deployment of the 22nm technology node. While several studies have been undertaken to estimate the lithography process costs for volume production with the aforementioned technologies, these studies have provided only a partial analysis since they have not taken into account the impact on design density and product yield.In this paper we use the cost-per-good-die metric in order to capture process costs as well as yield and design density. We have developed a framework that estimates the lithography cost-per-good-die for SRAM arrays and have applied it to evaluate the economical feasibility of the various lithography strategies under consideration for the 22nm technology node. Specifically, we compare the cost-per-good-die for different 32MB SRAM arrays, each optimized for a different lithography solution. Our analysis shows that the selection of the best lithography strategy is both layer and volume specific. The use of DPT solutions is recommended for Active and Contact layers. The use of Intf is recommended for layers such as Poly, Metals and Vias in the case of low volume products. For medium to high volume products the use of SMO is recommended for Poly, Metals and Vias. This paper provides quantifies of economic benefit of the proposed lithography strategy.
机译:极紫外光刻技术(EUVL)无法用于22nm技术节点的批量生产,这为主流光刻解决方案创造了巨大空间。为了填补这一空白,先前被认为在技术和经济上不可行的替代光刻解决方案,例如双图案技术(DPT),源掩模优化(SMO),大规模并行直写电子束(MEBM)和干涉辅助光刻(正在提议,开发和采用Intf)以确保及时部署22nm技术节点。尽管已经进行了一些研究来估计使用上述技术进行批量生产的光刻工艺成本,但是这些研究仅提供了部分分析,因为它们没有考虑对设计密度和产品良率的影响。 在本文中,我们使用“每模成本”度量标准来捕获工艺成本以及成品率和设计密度。我们已经开发了一个框架,可以估算SRAM阵列的每片平版印刷术的光刻成本,并将其用于评估22nm技术节点所考虑的各种光刻策略的经济可行性。具体来说,我们比较了不同32MB SRAM阵列的每片模具成本,每种阵列针对不同的光刻解决方案进行了优化。我们的分析表明,最佳光刻策略的选择既取决于层又取决于体积。建议对活动层和接触层使用DPT解决方案。对于小批量产品,建议将Intf用于诸如Poly,Metals和Vias等层。对于中到大批量产品,建议对Poly,Metals和Vias使用SMO。本文提供了所提出的光刻策略的经济利益的量化。

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